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LH5P8128
FEATURES * 131,072 x 8 bit organization * Access times (MAX.): 60/80/100 ns * Cycle times (MIN.): 100/130/160 ns * Single +5 V power supply * Power consumption: Operating: 572/385/275 mW (MAX.) Standby (CMOS level): 1.1 mW (MAX.) * TTL compatible I/O * Available for auto-refresh and self-refresh modes * 512 refresh cycles/8 ms * Compatible with standard 1M SRAM pinout * Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 8 x 20 mm2 TSOP (Type I) DESCRIPTION
The LH5P8128 is a 1M bit Pseudo-Static RAM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology. A PSRAM uses on-chip refresh circuitry with a DRAM memory cell for pseudo static operation which eliminates external clock inputs, while having the same pinout as industry standard SRAMs. Moreover, due to the functional similarities between PSRAMs and SRAMs, existing 128K x 8 SRAM sockets can be filled with the LH5P8128 with little or no changes. The advantage is the cost savings realized with the lower cost PSRAM. The LH5P8128 PSRAM has the ability to fill the gap between DRAM and SRAM by offering low cost, low power standby and a simple interface.
CMOS 1M (128K x 8) Pseudo-Static RAM
PIN CONNECTIONS
32-PIN DIP 32-PIN SOP TOP VIEW
RFSH A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 CE2 R/W A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
5P8128-1
Figure 1. Pin Connections for DIP and SOP Packages
32-PIN TSOP (Type I) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 R/W CE2 A15 VCC RFSH A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
NOTE: Reverse bend available on request.
5P8128-1A
Figure 2. Pin Connections for TSOP Package
1
LH5P8128
CMOS 1M (128K x 8) Pseudo-Static RAM
16 GND 32 VCC A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 A7 A8 A9 6 5 27 26 ROW ADDRESS BUFFER EXT/INT ADDRESS MUX ROW DECODER SENSE AMPS I/O SELECTOR DATA IN BUFFER 13 I/O0 14 I/O1 15 I/O2 17 I/O3 18 I/O4 19 I/O5 20 I/O6 DATA OUT BUFFER 21 I/O7
VBB GENERATOR
COLUMN ADDRESS BUFFER
COLUMN DECODER
A10 23 A11 25 A12 4 A13 28 A14 3 A15 31 A16 2
REFRESH ADDRESS COUNTER
MEMORY ARRAY
CE1 22 CE2 30
CLOCK GENERATOR
REFRESH CONTROLLER RFSH 1 OE 24 R/W 29
REFRESH TIMER
NOTE: Pin numbers apply to the 32-pin DIP or SOP.
5P8128-2
Figure 3. LH5P8128 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A16 R/W OE
Address input Read/Write input Output Enable Input
CE1, CE2 RFSH I/O0 - I/O7
Chip Enable input Refresh input Data input/output
2
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8128
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Applied voltage on any pins Output short circuit current Power dissipation Operating temperature Storage temperature
VT IO PD Topr Tstg
-1.0 to +7.0 50 600 0 to +70 -55 to +150
V mA mW C C
1
NOTE: 1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage Input voltage
VCC GND VIH VIL
4.5 0 2.4 -1.0
5.0 0
5.5 0 VCC + 0.3 0.8
V V V V
CAPACITANCE (TA = 0 to +70C, f = 1MHz, VCC = 5.0 V 10%)
PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT
A0 - A16 Input capacitance R/W, OE CE1, CE2 RFSH Input/output capacitance I/O0 - I/O7
CIN1 CIN2 CIN3 CIN4 COUT1
8 5 5 5 10
pF pF pF pF pF
DC CHARACTERISTICS (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
LH5P8128-60 Operating current LH5P8128-80 LH5P8128-10 Standby current Self-refresh average current Input leakage current I/O leakage current Output HIGH voltage Output LOW voltage
NOTES: 1. Specified values are with outputs open. 2. Depends on the cycle time. 3. CE1 = VIH, RFSH = VIH 4. CE1 = VCC - 0.2 V, RFSH = VCC - 0.2 V 5. CE1 = VIH, RFSH = VIL 6. CE1 = VCC - 0.2 V, RFSH = 0.2 V
104 ICC1 tRC = tRC (MIN) 70 50 ICC2 ICC3 ILI ILO VOH VOL 0 V VIN 6.5 V 0 V except on test pins 0 V VOUT VCC + 0.3 V Output in highimpedance state IOUT = -1 mA IOUT = 4 mA -10 -10 2.4 0.4 1 0.2 1 0.2 10 10 mA mA A A V V 1, 3 1, 4 1, 5 1, 6 mA 1, 2
TTL Input CMOS Input TTL Input CMOS Input
3
LH5P8128
CMOS 1M (128K x 8) Pseudo-Static RAM
1,2,3
AC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL
LH5P8128-60 MIN. MAX.
LH5P8128-80 MIN. MAX.
LH5P8128-10 MIN. MAX.
UNIT
NOTE
Random read, write cycle time Read modify write cycle time CE pulse width CE precharge time Address setup time Address hold time Read command setup time Read command hold time CE access time OE access time CE to output in Low-Z OE to output in Low-Z Output enable from end of write Chip disable to output in High-Z Output disable to output in High-Z Write enable to output in High-Z OE setup time OE hold time Write command pulse width Write command setup time Write command hold time Data setup time from write Data setup time from CE Data hold time from write Data hold time from CE Transition time (rise and fall) Refresh time interval Refresh command hold time Auto refresh cycle time Refresh delay time from CE Refresh pulse width (Auto refresh) Refresh precharge time (Auto refresh) Refresh pulse width (Self refresh) CE delay time from refresh precharge (Self refresh)
tRC tRMW tCE tP tAS tAH tRCS tRCH tCEA tOEA tCLZ tOLZ tWLZ tCHZ tOHZ tWHZ tOES tOEH tWP tWCS tWCH tDSW tDSC tDHW tDHC tT tREF tRHC tFC tRFD tFAP tFP tFAS tFRS
100 165 60 40 0 15 0 0
10,000
130 195 80 40 0 20 0 0
10,000
160 235 100 50 0 25 0 0
10,000
60 25 20 0 0 20 20 20 0 10 30 30 40 25 25 0 0 3 15 100 30 30 30 8,000 140 8,000 0 10 30 30 50 30 30 0 0 3 15 130 40 30 30 8,000 160 20 0 0
80 30 20 0 0 25 25 25 0 10 30 30 60 35 35 0 0 3 15 160 50 8,000 30 30 8,000 190
100 35
30 30 30
35 8
35 8
35 8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns
4 4
5 5
6 6 6 6
8,000
NOTES: 1. In order to initialize the circuit, CE1 should be kept at VIH or CE2 should be kept at VIL for 100 s after power-up, followed by at least 8 dummy cycles. 2. AC characteristics are measured at t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right). 4. Address is latched at the negative edge of CE1 or at the positive edge of CE2. 5. Measured with a load equivalent to 2TTL + 100 pF. 6. Data is latched at the positive edge of W/R or at the positive edge of CE1 or at the negative edge of CE2.
INPUT
2.4 V 0.8 V
2.6 V 0.6 V 2.2 V 0.8 V
OUTPUT
5P8128-3
Figure 4. AC Characteristics
4
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8128
tRC tP VIH VIL tCE
CE1
CE2
VIH VIL tAS tAH
ADDRESS INPUT
A0 - A16
VIH VIL
OE
VIH VIL tRCS VIH VIL tOEA tCEA tOLZ tCLZ VOH VOL tFP tFRS VIH VIL
5P8128-4
tRCH
R/W
tOHZ
tCHZ
I/O0 - I/O7
VALID-DATA OUTPUT
tRHC
tRFD
RFSH
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 5. Read Cycle
5
LH5P8128
CMOS 1M (128K x 8) Pseudo-Static RAM
tRC tP VIH VIL tCE
CE1
CE2
VIH VIL tAS tAH
ADDRESS INPUT
A0 - A16
VIH VIL tOES VIH VIL
tOEH
OE
tWCS tWCH tWP
R/W
VIH VIL tDSW tDSC tDHW tDHC
V I/O0 - I/O7 VOH OL tFP tFRS VIH VIL tRHC
DATA INPUT
tRFD
RFSH
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P8128-5
Figure 6. Write Cycle 1 (OE = HIGH)
6
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8128
tRC tP VIH VIL tCE
CE1
CE2
VIH VIL tAS tAH
ADDRESS INPUT
A0 - A16
VIH VIL
OE
VIH VIL tWCS tWCH tWP
R/W
VIH VIL tDSW tDSC VIH VIL tWHZ tDHW tDHC
DIN
VALID DATA INPUT
tOLZ tWLZ tCHZ
I/O0 - I/O7
tCLZ V DOUT VOH OL tFP tFRS VIH VIL tRHC
tOHZ
tRFD
RFSH
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P8128-6
Figure 7. Write Cycle 2 (OE Clock)
7
LH5P8128
CMOS 1M (128K x 8) Pseudo-Static RAM
tRC tP VIH VIL tCE
CE1
CE2
VIH VIL tAS tAH
ADDRESS INPUT
A0 - A16 OE
VIH VIL VIH VIL
tWCS tWCH tWP
R/W
VIH VIL tDSW tDSC VIH VIL tWHZ tDHW tDHC
DIN
VALID DATA INPUT
tCHZ tWLZ
I/O0 - I/O7
tCLZ VOH VOL tFP tFRS VIH VIL tRHC
DOUT
tRFD
RFSH
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P8128-7
Figure 8. Write Cycle 3 (OE = LOW)
8
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8128
tRMW tP VIH VIL
CE1
CE2
VIH VIL tAS tAH
A0 - A16
VIH VIL VIH VIL tRCS
ADDRESS INPUT
OE
tWCS tWP
R/W
VIH VIL tOEA tCEA VIH VIL tOLZ tWHZ tOHZ tWLZ tDSW tDSC tDHW tDHC
DIN
DATA INPUT
tCHZ
I/O0 - I/O7
tCLZ VOH VOL tFP tFRS VIH VIL tRHC
DOUT
DATA OUTPUT
tRFD
RFSH
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P8128-8
Figure 9. Read-Modify-Write Cycle
9
LH5P8128
tRC tP VIH VIL
CMOS 1M (128K x 8) Pseudo-Static RAM
tCE
CE1
CE2
VIH VIL tAS tAH
ADDRESS INPUT
A0 - A8
VIH VIL
tOEH VIH VIL tOES tRCS tRCH
OE
R/W I/O0 - I/O7
VIH VIL VOH VOL tFP tFRS VIH VIL
5P8128-9
HIGH-Z
tRFD tRHC
RFSH
NOTE: A9 - A16 = Don't Care.
Figure 10. CE Only Refresh
CE1
VIH VIL
CE2 OR CE1
VIH VIL
VIH VIL
CE2
VIH VIL tRFD tFP tFAS tFRS tRHC
RFSH I/O0 - I/O7
VIH VIL VOH VOL HIGH-Z
NOTE: OE, R/W, A0 - A16 = Don't Care.
5P8128-10
Figure 11. Self Refresh Cycle
10
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8128
CE1
VIH VIL
CE2 OR CE1
VIH VIL
VIH VIL tFC tFC
CE2
VIH VIL tRFD tFP tFAP tFP tFAP tRHC tFP
V RFSH VOH OL I/O0 - I/O7 VOH VOL HIGH-Z
NOTE: OE, R/W, A0 - A16 = Don't Care.
5P8128-11
Figure 12. Auto Refresh Cycle
11
LH5P8128
CMOS 1M (128K x 8) Pseudo-Static RAM
PACKAGE DIAGRAMS
32DIP (DIP032-P-0600)
32 17
DETAIL
13.45 [0.530] 12.95 [0.510]
1 41.30 [1.626] 40.70 [1.602]
16 0.30 [0.012] 0.20 [0.008]
0 TO 15
4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT
15.24 [0.600] TYP.
DIMENSIONS IN MM [INCHES]
32DIP
32-pin, 600-mil DIP
32SOP (SOP032-P-0525)
1.27 [0.050] TYP. 1.40 [0.055] 17
0.50 [0.020] 0.30 [0.012]
32
11.50 [0.453] 11.10 [0.437]
14.50 [0.571] 13.70 [0.539]
12.50 [0.492]
1 20.80 [0.819] 20.40 [0.803]
16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
32SOP
32-pin, 525-mil SOP
12
CMOS 1M (128K x 8) Pseudo-Static RAM
LH5P8128
32TSOP (Type I) (TSOP032-P-0820)
0.30 [0.012] 0.10 [0.004] 32 0.50 [0.020] TYP. 17
18.60 [0.732] 18.20 [0.717]
20.30 [0.799] 19.70 [0.776]
19.00 [0.748]
1 8.20 [0.323] 7.80 [0.307]
16 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000]
0.15 [0.006]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
32TSOP
32-pin, 8 x 20 mm2 TSOP (Type I)
ORDERING INFORMATION
LH5P8128 Device Type X Package - ## Speed 60 60 80 80 10 100 Access Time (ns)
Blank 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) T 32-pin, 8 x 20 mm2 TSOP (Type I) (TSOP032-P-0820) TR 32-pin, 8 x 20 mm2 TSOP (Type I) Reverse bend (TSOP032-P-0820) CMOS 1M (128K x 8) Pseudo-Static RAM Example: LH5P8128N-60 (CMOS 1M (128K x 8) Pseudo-Static RAM, 60 ns, 32-pin, 525-mil SOP)
5P8128-12
13

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